In a prior art configuration where a signal source, such as a clock source, provides a common signal to a number of separate receiving devices, such as gates within a single integrated circuit (IC), IC's within a single board, or separate circuit boards within a chassis, the signal generated at the output of the signal source arrives at an input port of each of the various receiving devices at various times determined by the propagation delay of the signal through the conductors coupling the signal source to the particular receiving device. Hence, the signal will most likely reach each receiving device at a slightly different time due to a different propagation delay being associated with each receiving device. This type of prior art circuit is shown in FIG. 1, where signal source 10 provides, for example, a common clock pulse to each of the receiving devices 1, 2, 3 and 4. As seen from FIG. 1, the generated clock pulse must be transmitted through a different length of conductor for each receiving device, resulting in a different signal propagation delay for each receiving device.
In general, electronic equipment which use the rise or fall of a clock pulse to initiate execution of a next instruction or a change in logic states is able to absorb a range of clock pulse propagation delays wherein the first receiving device to receive a clock pulse is not affected by the delay incurred by the longer propagation delay associated with a more distant receiving device. However, higher clock rates are ultimately constrained by the magnitude of the range of signal propagation delays when the receiving devices must communicate with each other or transmit a reply back to a common device, such as a microprocessor, where the microprocessor makes a decision based on the concurrent inputs of two or more receiving devices. Considering that the propagation speed through a copper conductor is approximately 0.5 feet per nanosecond and the length of conductor between one receiving device and another may be several feet, and also considering that propagation delay is further increased by capacitances and inductances along the wire, it can easily be understood how logic designers must take into account the various propagation delays between a clock source and the receiving devices when determining a maximum clock rate. Additionally, allowable range of propagation delays is severely limited when each receiving device requires a different time to execute an instruction initiated by the clock pulse and the concurrent outputs of the receiving devices must be further processed by, for example, a microprocessor.
As market demand for computing power seems insatiable, computer systems (especially PC's and workstations) continue to get more and more powerful which, today, is usually accomplished by reducing the system's average instruction cycle time. This means using fewer clock cycles per instruction and/or using a faster clock. With the emergence of processors which approach one instruction per clock, future advances in system performance will continue to depend on increasing the system clock frequency. However, system clock frequency remains constrained by the range of propagation delays between the clock source and the receiving devices.